Language Breakdown
Lines of code distribution across 18 owned repositories
174K
Total LOC
Tcl
80,826 lines
46.5%
N/A
Perl
41,629 lines
24.0%
N/A
SourcePawn
23,071 lines
13.3%
N/A
Verilog
19,401 lines
11.2%
N/A
C
7,901 lines
4.6%
N/A
Other
816 lines
0.5%
N/A
T
T-Shaped Developer
T-shapedDeep in Tcl with broad versatility
Tcl
Perl
SourcePawn
Verilog
C
Collaboration Network
Global Impact visualization
Repos
19
PRs
0
Growth
+18%
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Top Repositories
asap_7nm_Xschem
10
2
finfet_characterestics
1
0
SourcePawn
SRAM
1
0
Tcl
avsd_iiitdm_7nm_dac
1
0
Perl
XOR_opencircuits_fullCustom
1
0
Tcl
Opensource_Inverter_Full_custom
1
0
Tcl
2scomplement_8bit_adder
1
0
Verilog
edgedetection_verilog
Th following verilog code is used to descibe a hardware for edge detection. Icarus verilog is the compiler used
1
0
Verilog
jkflipfop_from_dflipflop
1
0
Verilog
UnivesalCounter-using-Verilog-HDL
1
0
Verilog
Open Source Impact
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0 merged PRs
No external contributions found.